Interface Design

BAMRA APPLICATION LOGIC PROGRAM INTERFACE

Interface Design Presentation

BAMRA APPLICATION LOGIC PROGRAM

PROGRAM TITLE

 

PROGRAM TITLE DISPLAYED ON SCROLLING DISPLAY OF MLKII

FOR C1 PROGRAM

MICROLOK_II PROGRAM BMB_C1_S01;

FOR C2 PROGRAM

MICROLOK_II PROGRAM BMB_C2_S01;

 

LOCAL BIT DEFINITIONS

BOARD:  J1

ADJUSTABLE ENABLE:  1

TYPE:  NV.IN32.OUT32

NV.OUTPUT:

1DGKE,           1RGKE,                   1UGKE,                  1.C1AJKE,

C1HGKE,        SH3_OFFKE,        SH3_ONKE,          SH3AJKE,

SH5_OFFKE,  SH5_ONKE,         SH5AJKE,              8DGKE,

8RGKE,            8.SH8AJKE,         SH8_OFFKE,        10HGKE,

10RGKE,          10.SH10AJKE,      SH10_OFFKE,      12HGKE,

12RGKE,           12.SH12AJKE,       SH12_OFFKE,     14DGKE,

14RGKE,          16DGKE,                  16RGKE,              UD_DGKE,

UD_HGKE,      UID_DGKE,           UID_HGKE;

 

BOARD:  J1

ADJUSTABLE ENABLE:  1

TYPE:  NV.IN32.OUT32

NV.INPUT:

1GN,            C1GN,             SH3GN,          SH5GN,

8GN,           SH8GN,         10GN,             SH10GN,

12GN,         SH12GN,       14GN,              16GN,

14ATUN,    DD1UN,         DD2UN,        CLUN,

DLUN,        DMUN,          UMUN,         SDUN,

21WN,         22WN,           23WN,          25WN,

SPARE,       SPARE,          28KTN,        24LXN,

CH1N,         CH2N,            CH3N;

 

BOARD:  J1

ADJUSTABLE ENABLE:   1 

TYPE:  OUT16

OUTPUT:

1DR,            1HR,             C1HR,              1BUR,

1CUR,         SH3HR,       6DR,                 6HR,

SH6HR,      8HR,           SH8HR,            12DR,

SH15HR,     UD_DR,      UID_DR,       UID_HHR;

 

BOARD:  J7

ADJUSTABLE ENABLE:  1 

TYPE:  IN16

INPUT:

SH15_OFFECR,            SH15_ONECR,                  UD_DECR,               UD_HHECR,

UD_HECR,                     UID_DECR,                      UID_HHECR,           UID_HECR,

16NWK1R,                      16RWK1R,                            17NWK1R,                17RWK1R,

18NWK1R,                     18RWK1R,                             19NWK1R,                19RWK1R;

 

SERIAL BIT DEFINITIONS

ADDRESS:  20

ADJUSTABLE ENABLE:  1

OUTPUT:

// VITAL SERIAL OUTPUT TO I/O GATHERER MICROLOK

// MAXIMUM 128 OUTPUT BITS (16BYTES) CAN BE DEFINED IN THIS ADDRESS SECTION.

IVSL_COMOK.ISO,

1DR.ISO,                 1HR.ISO,                  C1HR.ISO,               1BUR.ISO,

1CUR.ISO,              SH3HR.ISO,            6DR.ISO,                 6HR.ISO,

SH6HR.ISO,            8HR.ISO,               SH8HR.ISO,           12DR.ISO,

SH15HR.ISO,        UD_DR.ISO,           UID_DR.ISO,       UID_HHR.ISO,

16WNR.ISO,          16WRR.ISO,            17WNR.ISO,          17WRR.ISO,

18WNR.ISO,           18WRR.ISO,           19WNR.ISO,           19WRR.ISO;

 

ADDRESS:  20

ADJUSTABLE ENABLE:  1

INPUT:

// VITAL SERIAL INPUT TO I/O GATHERER MICROLOK

// MAXIMUM 128 INPUT BITS (16BYTES) CAN BE DEFINED IN THIS ADDRESS SECTION.

1DECR.ISI,                   1HECR.ISI,                    1RECR.ISI,                    C1HECR.ISI,

1UECR.ISI,                   6DECR.ISI,                    6HECR.ISI,                    6RECR.ISI,

8HECR.ISI,                  8RECR.ISI,                    12DECR.ISI,                   12RECR.ISI,

UD_DECR.ISI,         UD_HHECR.ISI,            UD_HECR.ISI,              UID_DECR.ISI;

 

SERIAL LINK PARAMETERS

LINK:     IVSL                 // ANY USER SELECTED TEXT STRING

ADJUSTABLE ENABLE:              1

PROTOCOL:                   MICROLOK.MASTER              // GENISYS.SLAVE, GENISYS.MASTER,

                                                                                                     // MICROLOK.SLAVE, MICROLOK.MASTER

// PHYSICAL PORT DEFINITIONS

ADJUSTABLE POINT.POINT:                1;                    // 0-FOR SLAVE PORT, 1-FOR MASTER PORT

ADJUSTABLE PORT:                                2;                   // PORT 1 TO 4

ADJUSTABLE BAUD:                          9600;                // 150-19200 IN STEPS

ADJUSTABLE STOPBITS:                      1;                    // 1 OR 2 (DEFAULT 1)

ADJUSTABLE PARITY:                     NONE;              // ODD, EVEN MARK, SPACE, NONE(DEFAULT

ADJUSTABLE KEY.ON.DELAY:         12;                   // 0-280 FOR GENISYS & 8-280 FOR MLK

ADJUSTABLE KEY.OFF.DELAY:       12;

 

// PROTOCOL DEFINITIONS

ADJUSTABLE STALE.DATA.TIMEOUT:               4:SEC;               // KEEP DEFAULT VALUE – 4 FOR MICROLOK

// AND 30:SEC FOR GENISYS PROTOCOL)

ADJUSTABLE POLLING.INTERVAL:                  50:MSEC;           // DEFAULT: 50 MSEC

ADJUSTABLE MASTER.TIMEOUT:                     500:MSEC;         // DEFAULT: 500MSEC,

// 30-5000MSEC – MICROLOK PROTOCOL

// 30-25000MSEC – GENISYS PROTOCOL

 

 

LINK:                        NVLMP              //(ANY USER SELECTED TEXT STRING)

ADJUSTABLE ENABLE:               1

PROTOCOL:                GENISYS.SLAVE                    // GENISYS.SLAVE, GENISYS.MASTER,

                                                                                               // MICROLOK.SLAVE, MICROLOK.MASTER

                                                                                              // PHYSICAL PORT DEFINITIONS

ADJUSTABLE POINT.POINT:    0;                         // 0-FOR SLAVE PORT, 1-FOR MASTER PORT

ADJUSTABLE PORT:                     3;                         // PORT 1 TO 4

ADJUSTABLE BAUD:                  9600;                  // 150-19200 IN STEPS

ADJUSTABLE STOPBITS:             1;                       // 1 OR 2 DEFAULT 1

ADJUSTABLE PARITY:            NONE;                  // ODD, EVEN MARK, SPACE, NONE(DEFAULT

ADJUSTABLE KEY.ON.DELAY:    64;                // 0-280 FOR GENISYS & 8-280 FOR MLK

ADJUSTABLE KEY.OFF.DELAY:  64;

 

// PROTOCOL DEFINITIONS

ADJUSTABLE STALE.DATA.TIMEOUT:      10:SEC;               // DEFAULT VALUE – 4 FOR MICROLOK

// AND 30:SEC FOR GENISYS PROTOCOL

ADJUSTABLE CARRIER.MODE:                   CONSTANT;      // CONSTANT OR KEYED

ADJUSTABLE CRC.SIZE:                                 16;                        // 16 OR 24 BITS, DEFAULT:16BITS

 

BOOLEAN BIT DEFINITION

BOOLEAN BITS

1.C1EGNR,                 C1UCSR,                    2.C2EGNR,                C2UCSR,

1ANNR,                      1BNNR,                         1CNNR,                    C1ANNR,

1ANRR,                      1BNRR,                         1CNRR,                     C1ANRR,

OV5NNR,                OV6NNR,                       OV7NNR,                 OV1_8NNR,

OV5JSLR,                OV5JR,                            OV5SR,                        OV6JSLR,

16NLR,                     16RLR,                              17NLR,                         17RLR,

1UCR,                       C1UCR,                             2UCR,                          C2UCR,

1.C1TSR,                  2.C2TSR,                           SH3TSR,                    SH4TSR,

1.C1ALSR,               2.C2ALSR,                        SH3ALSR,                  SH4ALSR,

1.C1UYR1,                 1.C1UYR2,                        1.C1UYR3,                  1.C1UYR4,

CH1LR,                       CH1NR,                           CH1RR,                           CH2LR,

CPS.STATUSJ2,         CPSJR,                       SYSINITTMR,             SYSINITTMR1,

 

TIMER BIT DEFINITION

TIMER BITS

EW_N.R_CR:                       SET=0:SEC                     CLEAR=1:SEC;

EUUYNPR:                            SET=0:SEC                     CLEAR=1:SEC;

OV5JSLR:                              SET=0:SEC                     CLEAR=1:SEC;

OV5JBPR:                              SET=0:SEC                     CLEAR=1:SEC;

OV5JR:                                   SET=120:SEC                  CLEAR=0:SEC;

1.C1JSLR:                                SET=0:SEC                     CLEAR=1:SEC;

1.C1JBPR:                                SET=0:SEC                      CLEAR=1:SEC;

1.C1JR:                                     SET=120:SEC                  CLEAR=0:SEC;

CPS.STATUSJ2:                    SET=0:SEC                      CLEAR=2:SEC;

SYSINITTMR:                        SET=130:SEC                  CLEAR=0:SEC;

FLASH:                                     SET=700:MSEC              CLEAR=700:MSEC;

 

LOG BIT DEFINITION

LOG BITS

1.C1EGNR,               C1UCSR,                    2.C2EGNR,                 C2UCSR,

   1ANNR,                   1BNNR,                         1CNNR,                    C1ANNR,

   1ANRR,                    1BNRR,                        1CNRR,                     C1ANRR,

 OV5NNR,                  OV6NNR,                    OV7NNR,                 OV1_8NNR,

 OV5JSLR,                  OV5JR,                         OV5SR,                     OV6JSLR,

  16NLR,                         16RLR,                          17NLR,                        17RLR,

     1UCR,                        C1UCR,                           2UCR,                        C2UCR,

    1.C1TSR,                  2.C2TSR,                        SH3TSR,                   SH4TSR,

   1.C1ALSR,                2.C2ALSR,                    SH3ALSR,                SH4ALSR,

   1.C1UYR1,                1.C1UYR2,                      1.C1UYR3,               1.C1UYR4,

     CH1LR,                     CH1NR,                            CH1RR,                   CH2LR,

 CPS.STATUSJ2,           CPSJR,                     SYSINITTMR,         SYSINITTMR1,

 

CONSTANT BIT DEFINITION

BOOLEAN:

ONE=1;          ZERO=0;

 

NUMERIC:

INSTALLATION_ADDRESS                             = 51721;

APPLICATION_DATA_VERSION                   = 07;

EXECUTIVE_SOFTWARE_VERSION           = 401;

 

SYSTEM CONFIGURATION

SYSTEM

ADJUSTABLE DEBUG_PORT_ADDRESS:                             1;

ADJUSTABLE DEBUG_PORT_BAUDRATE:                     19200;

ADJUSTABLE LOGIC_TIMEOUT:                                      3000:MSEC;                //100MSEC-5SEC

STEP 100MSEC

ADJUSTABLE DELAY_RESET:                                             100:MSEC;                //0-10SEC STEP

100MSEC

 

NUMERIC BIT DEFINITION

USER NUMERIC

CONFIGURATIONELEMENT_ADDRESS:                 “INSTALLATION ADDRESS”;

CONFIGURATIONELEMENT_APPLICATION_DATA_VERSION:

“APPLICATION DATA VERSION”;

CONFIGURATIONELEMENT_EXECUTIVE_SOFTWARE_VERSION:

“EXECUTIVE SOFTWARE VERSION”;

 

LOGIC SECTION

                Panel PC Change over Logic

               Operator PC Serial Input Timer Logic

               Push Button Logic

               Emergency Operation Push Button Logic

               EGNR & UCSR Logic

               Signal NNR & NRR Logic

               Overlap Logic

Point NLR & RLR Logic

Point Chain Logic

Point WNR & WRR Logic

Point Detection Logic

UCR Logic

TSR Logic

Signal ALSR, JSLR, UYR Logic

 

Point WLR Logic

Signal HR & DR Logic

Crank Handle & Siding Control Logic

Level Crossing Control Logic

Block Logic

Axle Counter Reset Logic

Signal Indication Logic

Point & Overlap Indication Logic

Track Circuit Indication Logic

Signal Failure Alarm Logic

Point Failure & Button Stuck Alarm Logic

System Initialization & Link Status Logic

FCOR Logic

Cardfile Identification Logic

 

COMPILATION TECHNIQUES

This chapter describes the command line operation of the Microlok II logic compiler and the formats of its output files. This chapter also covers the specific consistency checks that the compiler performs on the user’s application. The compiler is a 32-bit Windows compatible program. Details of the program language are included in chapter 3.

 

4.2 DEFAULT EXTENSIONS

If the user does not supply filename extensions, the compiler will assign the following extensions by default:

File Type Extension                   Extension

Application Source                    ML2

Listing                                            MLL

Application                                   MLP

 

4.3 RUNNING THE COMPILER

The compiler is configured in Text Editor Program. User can run the compiler by selecting proper compiler option in “Tool” menu of Editplus Program.

The compiler will return a non-zero value to the command processor if there were any errors during compilation or if there was any problem with the form or content of the command line. Otherwise, it will return zero.

The result of compilation will be displayed at the bottom of Editplus Program window if Text Editor is configured to do so.

 

4.5 LISTING INFORMATION

The listing file provides information about compiler-generated information in the application, as well as reports about usage of various resources defined in the application. The listing will show the date of compilation, and the version number and date of the compiler.

 

4.5.1 Source Listing

First in the listing is the source listing. It shows warnings, severe warnings, and errors as they relate to source lines. The listing also shows relevant statement numbers assigned by the compiler. Each line of the source listing has the form:

<line number> [<statement number>] <text of original source line>

If a line does not have an associated statement number, the <statement number> portion of the line will appear blank. Lines that will have statement numbers will be those with ASSIGN, NV.ASSIGN, EVALUATE, NV.EVALUATE, or IF statements.

 

Source Listing: Cont’d

The compiler generates statement numbers to aid in debugging. Errors and warnings reported by the executive refer to statements by statement number.

Warning, severe warning, and error messages in addition to any additional information that they may generate will be interspersed between the source listing lines.

Application Image Identification

After the source listing, the compiler presents enough information to correctly match the listing to the application. This information consists of:

Target type — Microlok II or MicroCab II

CRC of application image as used by the   Microlok II Maintenance tool.

Checksum that would be seen on Flash   EPROM programmer.

 

Unusual Numeric Summary

To call attention to the numeric variables with non-default minimum, maximum, error, or initial values, the compiler generates a table listing the following:

1.Numeric variable name

2.Numeric variable id number

3.Minimum value

4.Maximum value

5.Error value

6.Initial value

 

Unused Variable Summary

In order to call attention to variables that the system or the user defined but never used in logic, the compiler will generate a list of such bits. I/O points defined as SPARE will not appear in this list. It looks like:

<id number> <id name> <bit type>

 

Unassigned User-Defined Variable Summary

In order to call attention to variables that the user defined but were never assigned a value, the complier will generate a list of unassigned user-defined variables. This list will not include user defined INPUTs, because inputs cannot be the object of an ASSIGN or NV.ASSIGN statement.

The list looks like:
<id number> <id name> <bit type>

 

Unused User-Defined Variable Summary

In order to call attention to variables that the user defined but did not use, the complier will generate a list of unused user-defined variables.

The list looks like:

<id number> <id name> <bit type>

 

Bit Usage Summary

Information about each bit used in the system is also displayed in a table. This table lists the id number and id name. Also listed is the number of times it is used as a front contact, a back contact, a block trigger, a table trigger or a coded output.

Variables in numeric blocks may be assigned to multiple times. If the bit has multiple assignments to it, the next column shows the number of assignments. If there is only one, this column is blank.

After this, the compiler will list which type of target the variable is: assign, non-vital assign, input, user item, table or system.

 

Following this is the vitality of the bit. The table will indicate if the bit is vital or non-vital.

Next the nature of the definition is displayed. It indicates if the bit is an internal, user

configuration, output or input.

For example, part of a table might look like:

 

ID#      ID Name        FRONT           BACK         BLOCK          TABLE         CODE        ASGN          TARG               VITAL

14             34R                   0                       0                  0                      0                      0                            ASGN  VITAL       OUT

123          1ASR                  1                        3                 0                       0                     0                             ASGN  VITAL       INT

125          TRIG                  0                       0                  1                       1                      0                             ASGN  VITAL       INT

126        ERROR               0                       0                  0                      0                      0             23           NASGN NON       INT

 

Board Summary

I/O boards are summarized as the name and type of the board as well as the state any configuration parameters belonging to it. Entries for all boards will show the state of the enable as defined in the application as well as its fixed or adjustable status.

 

Comm Link Summary

Comm Links are summarized as the name and protocol of the link as well as the state any configuration parameters belonging to it. Entries for all links will show the state of the enable as defined in the application as well as its fixed or adjustable status. Also, the enabled state of each of the stations on the link will be displayed.

 

COMPILER CHECKS

In the course of processing the source file, the compiler can generate errors, warnings, and severe warnings. Errors are generated in response to source code that cannot be interpreted by the compiler as a meaningful program. Severe warnings are generated when the user input can be interpreted as a usable program, but the compiler makes corrections to the source code. Sever warnings are intended to notify the programmer of what corrections the compiler has made. Warnings are generated for inputs that may cause safe, but unusable behavior.

The following are a few examples of source code problems that would cause the various classes of messages to occur: Warnings (an application image is generated and can be used): Any board or link defined as FIXED and disabled. Severe warnings (an application image is generated): The user must check any of the following conditions to determine if a problem will result:

*   Non-vital assignment to vital bit.

*  Non-vital evaluate to vital numeric.

*  Errors (an application image is not generated):

*  Syntax errors

*  Use of undefined bits

 

 

BAMRA APPLICATION LOGIC PROGRAM, PROGRAM TITLE, SERIAL BIT DEFINITIONS,SERIAL LINK PARAMETERS,BOOLEAN BIT DEFINITION,TIMER BIT DEFINITION, LOG BIT DEFINITION,CONSTANT BIT DEFINITION, NUMERIC BIT DEFINITION, Panel PC Change over Logic, Operator PC Serial Input Timer Logic, Push Button Logic, Emergency Operation Push Button Logic,  EGNR & UCSR Logic,Signal NNR & NRR Logic, Overlap Logic, COMPILATION TECHNIQUES,  RUNNING THE COMPILER,Source Listing ,Unassigned User-Defined Variable Summary,Bit Usage Summary

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